RHS Research Xilinx Artix-7 FPGA M.2 Development Board (A200T FPGA/1GB DDR)

Board (NITEFURY II) works as expected. Two clocks are available even when not using PCIE (100 MHz from PCIE on motherboard and 200 MHz for DDR). The 4 available IOs can be used for a UART/I2C/SPI device (successfully used them for a UART). JTAG works with a Digilent HS2 dongle. PCIE performance obviously depends on the motherboard.Support nice to haves for the future (hopefully through documentation/code on GitHub):- is there a ribbon cable available to use with the connector under the fan? This is likely not available since 4 IOs are 3.3v and the others are diff pairs at 2.5v. The 4 LVDS pairs might be useful for some high speed communication outside of PCIE.- it seems that there is a fan controller in the provided PCIE image, as deprogramming the FPGA/programming with a different image leads to fan undergoing some sort of hysteresis which can be disturbing. Documenting such controller would be useful (very likely thru an analog control from the xadc since there's no PWM pin).

The Artix-7 A200T in a decent speed grade is a very capable FPGA and the price on this board is less than the price of the chip alone. The catch is that few of the chips IOs are broken out directly and the main way to get data to the FGPA is over PCI. I have mine mounted in an external M2 to thunderbolt 4 case.The Nitefury II is the same hardware as the SQRL Acorn but that shouldn't put an FPGA hobbyist off because the Acorn failed because SQRL didn't deliver the software (including the bit stream) to act in tandem with a GPU to mine crypto. Google SQRL Acorn to find tools for using this board in addition to the makers.

Took considerable work to get the GitHub sample program to work in Vivaldo and so it would load on device. Seems to work. Shows up in pcie enumeration. Have not successfully gotten pcie communication to work yet though. Began working on another project.

impressive form factor with good number of LUTs/DSPs on FPGA, can be used to implement multiple soft cores and HW accelerators.IOs are limited but it can be workaround via PCIe XDMA.